1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically, to a semiconductor integrated circuit device including combined logic circuitry of CMOS (complementary metal oxide semiconductor) integrated circuit devices.
2. Background Art
Heretofore, as shown in FIG. 7, a method for elevating the speed of the critical path of logic circuitry using a low-threshold cell wherein a power source switching transistor is provided in a standard cell is disclosed in Non-Patent Document 1. FIG. 7 shows the basic configuration of a conventional MT (multiple threshold-voltage) cell, and (a) shows a two-input NAND cell, (b) shows a two-input NOR cell, and (c) shows a selection MT circuit. The MT cell can simultaneously achieve the high-speed operation of the circuit and a low leakage current in stand-by time.
However, the installation of an independent power switch in each cell limits the effective circuit area by indirect components, and the overhead in term of area (indirect costs) is large. For example, in order to minimize the effect of the added switching transistor, if the size of the switch is twice the size of the transistor to compose logic, the area of the cell is approximately doubled; however, the logical delay time is prolonged by about 20%. For limiting the deterioration of delay time to 10%, it is required to connect a switching transistor having a size of 4 to 5 times the size of the logic transistor.
A method to share a power switch by a plurality of standard cells is normally a method frequently used. Since all the power is not simultaneously consumed even if the switch is shared, the maximum current of the shared switch is smaller than the sum of the maximum currents of a cell. However, since the occurrence of simultaneous switching differs depending on signal patterns, the peak value of current consumption is varied. Therefore, since it is difficult to accurately estimate the peak value of current consumption and the quantity of delay deterioration caused by voltage drop due to switching, it is required to connect a sufficiently large switching transistor.
Therefore, a method for sharing a switch by standard cells themselves wherein no simultaneous switching is clearly known, such as sequential inverters, is proposed in Patent Document (Japanese Patent Laid-Open No. 2003-249563) (refer to FIG. 3 in the bulletin).
However, according to a conventional semiconductor integrated circuit described in the above Patent Document, there were the following two problems. Firstly, in designing a chip in the conventional semiconductor integrated circuit, the switching transistor must be later disposed. Therefore, the switching transistor cannot be disposed in the area where cells are crowded, or must be disposed in the position far from the cells, and there is a problem that the switching transistor cannot be disposed in the optimal position.
Secondly, in cells to be paired, when inverters continue back and forth (refer to FIG. 7 in the bulletin), the normal logic cell having no switch in the cell or the like must be disposed between the cells wherein inverters continue back and forth (refer to FIG. 3 in the bulletin), and there is another problem that the scope of application is limited.
As a conventional art document other than the above-described Patent Document, there is Non-Patent Document (Papers for ISLPED—International Symposium on Low Power Electronics and Design—, 2002, pp. 202-206).